Skyworks的Si536x系列提供以下功能和優(yōu)勢:

• 多達18路輸出，頻率組合最高可達2.75GHz，輸出格式可選，包括LVPECL、LVDS、CML、HCSL和LVCMOS。這些輸出閾值也可以定制，以支持非標準格式的芯片組。
• 無縫輸入時鐘管理，具有出色的輸入?yún)⒖紩r鐘切換性能，包括內(nèi)部和外部無中斷切換工作模式，分別支持35 ps和75 ps相位瞬變。
• 全套時鐘質(zhì)量指標和警報，提供時鐘故障監(jiān)控的全面可見性。
• 同類最佳的<-90dB電源抑制，使設計人員能夠減少噪聲濾波元件，從而實現(xiàn)更具成本效益的解決方案和簡化的物料清單。
• 在線可重構(gòu)性，使輸出頻率能夠在系統(tǒng)停機時動態(tài)變化。

設計師可以用Skyworks快速配置時鐘樹設計ClockBuilder Pro軟件。使用具有集成設計規(guī)則檢查、功耗估計和串擾向?qū)У闹庇^ClockBuilder Pro，設計人員可以在不到十分鐘的時間內(nèi)快速生成復雜的器件配置，從而最大限度地減少軟件開發(fā)開銷。

Skyworks OSCILLATOR aunched its latest portfolio of jitter attenuators for high-speed networking, communications and data center equipment forming the backbone of today’s internet infrastructure. These new products are designed to meet the performance requirements of high-speed networks deployed to carry 5G traffic and support new applications like AI and edge computing. The new Si536x product family complements Skyworks’ current Si539x jitter attenuating clocks to suit the specific timing needs of designers and vendors.

Increasing demand for data bandwidth is driving the need for 400G/600G/800G+ Ethernet links using high-speed 56G/112G/224G PAM-4 SerDes and coherent optical technologies for internet infrastructure and data center environments. The Dell’Oro Group forecasts that these data rates currently comprise half of the total Ethernet data center, with 800G expected to dominate by 2025.1 These high-speed systems require multiple clocks at different frequencies, signaling formats and voltage levels with ultra-low jitter.

To address this need, the Si536x product family provides frequency flexibility and clock tree on-a-chip integration in a compact clock IC solution with up to 18 clock outputs featuring <55 fs RMS jitter, enabling optimal transceiver performance. The increased jitter margin also helps de-risk product development and accelerate time to market for networking equipment vendors.

“Skyworks’ latest product family continues the company’s long-standing history of developing innovative timing solutions, featuring its ultra-low jitter DSPLL® architecture with MultiSynth™ ‘any-frequency’ clock synthesis,” said James Wilson, vice president and general manager of timing products at Skyworks<trans newtip="。“這些產(chǎn)品針對下一代高速通信設計，允許我們的客戶利用最高性能、最低抖動的時鐘。" "="" oldtip=". “These products address the next generation of high-speed communications’ designs, allowing our customers to take advantage of the highest performance, lowest jitter clocks available.” " style="box-sizing: border-box;">. “These products address the next generation of high-speed communications’ designs, allowing our customers to take advantage of the highest performance, lowest jitter clocks available.”